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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:09:26 04/13/2008 
-- Design Name: 
-- Module Name:    DisplayTest - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DisplayTest is
    Port ( memory_address : out  STD_LOGIC_VECTOR (17 downto 0);
           req_out : out  STD_LOGIC;
			  req_write : out  STD_LOGIC;
           write_data : out  STD_LOGIC_VECTOR (15 downto 0);
           wait_in : in  STD_LOGIC;
           clk : in  STD_LOGIC);
end DisplayTest;

architecture Behavioral of DisplayTest is

	type t_state is (s_clear, s_clear_wait, s_border, s_border_wait, s_end);
	signal state : t_state := s_clear;
	signal data : std_logic_vector (15 downto 0);
	signal address : std_logic_vector (17 downto 0);
	signal Haddr, Vaddr, pixel_address : std_logic_vector (18 downto 0);
	signal old_wait_in : std_logic;

begin

	write_data <= data;
	memory_address <= address;
	pixel_address <= ("000000000" & Haddr) + (Vaddr & "000000000") + ("00" & Vaddr & "0000000");

	test : process(clk)
	begin
		if rising_edge(clk) then
			old_wait_in <= wait_in;
			case state is
				when s_clear =>
					if address = x"32000" then
						state <= s_border;
					else
						state <= s_clear_wait;
						data <= (others=>'0');
						req_out <= '1';
						req_write <= '1';
					end if;
				when s_clear_wait =>
					req_out <= '0';
					req_write <= '0';
					if (old_wait_in & wait_in) = "00" then
						address <= address+1;
						state <= s_clear;
					end if;
				when s_border =>
					if Vaddr = 320 then
						state <= s_end;
					else
						address <= pixel_address(18 downto 1);
						Vaddr <= Vaddr+1;
						Haddr <= Haddr+2;   -- two pixels per word
						req_out <= '1';
						req_write <= '1';
						data <= (others=>'1');
						state <= s_border_wait;
					end if;
				when s_border_wait =>
					req_out <= '0';
					req_write <= '0';
					if (old_wait_in & wait_in) = "00" then
						state <= s_border;
					end if;
				when s_end =>
					state <= s_end;
			end case;
		end if;
	end process;

end Behavioral;

